In recent years, as semiconductor devices (LSIs: large scale integrated circuits) are becoming multi-layered, trace smoothness is studied due to processing constraints in CMP (chemical mechanical polishing) process and the like. Therefore, for example, in physical verification, density verification (a chip region is divided by a verification frame and the verification frame is moved stepwise by a predetermined width) was performed for verifying whether trace density is within a specific standard value or not. Then, if the trace density exceeds the specific standard value, trace layout is corrected.
In the conventional layout data verification method (design method) for the semiconductor device, even if the layout data passes the density verification with no error at a macro level, in chip-level density verification where the macro is loaded, a density error (density exceeding a standard value) may occur due to difference of starting origins (difference of how patterns are included in the density verification frame).
In this case, the macro is corrected for each product type so as to pass the density verification and, therefore, a man-hour is used every time the macro is corrected. Further, in such approach, when the same macro is loaded on another product type, the error may occur again and, therefore, this approach does not solve the problem.
In this connection, conventionally, in order to reduce the data amount to be checked and, thus, processing time for verifying layout data of a semiconductor device, there is proposed a layout data verification method of a semiconductor device, comprising the steps of: setting a graphic data extraction region including a width of a design standard value from an outside frame of a functional block; preparing extracted data by extracting pattern data at least a portion of which is included in the graphic data extraction region; preparing extracted data from other functional blocks in a similar manner; setting a trace data extraction region including a width of the design standard value from a boundary line of a trace block; preparing extracted trace data by extracting pattern data at least a portion of which is included in the trace data extraction region; and, then, performing design rule check on the whole semiconductor device based on all extracted data and trace extracted data (Japanese Laid-Open Patent Publication No. H06-125007).
As described above, as the LSIs are becoming multi-layered and the trace smoothness is studied from the process viewpoint such as the CMP process, there arises a need to ensure that trace density does not exceed a standard value (for example, 40% to 60%).
Then, in the conventional layout data verification method (design method) for the semiconductor device, the density verification (for example, density verification by dividing a chip region by a verification frame of a square shape of 100 μm×100 μm, and moving the verification frame sequentially by a predetermined step width such as 10 μm) is performed in a physical verification phase (DRC: design rule check).
FIGS. 1 to 4 are diagrams for describing problems in the conventional layout data verification method of the semiconductor device. In FIGS. 1 to 4, reference symbol 100 denotes a chip, 200 denotes a macro (macro A), O1 denotes an origin of the chip, O2 denotes an origin of the macro, and W denotes a density verification frame.
As illustrated in FIG. 1, for example, density verification of chip (semiconductor device: LSI) 100 is performed with reference to origin O1 of chip 100 by shifting (moving) density verification frame (for example, verification frame of a square shape of 100 μm×100 μm) W sequentially from this origin O1 by a predetermined step width (for example, 10 μm). Here, the density verification is typically performed on patterns in a region included in density verification frame W by shifting this density verification frame W by the predetermined step width from the lower left origin (O1) in the right or upper direction.
On the other hand, as illustrated in FIG. 2, density verification of macro (macro A) 200 (macro-level density verification) is typically performed with reference to origin O2 of macro 200 by shifting density verification frame W sequentially from this origin O2 by a predetermined step width.
However, when macro 200 is disposed on chip 100, macro 200 is disposed on an arbitrary position on chip 100 and, therefore, the density verification of chip 100 (chip-level density verification) is performed with reference to origin O1 of chip 100 that differs from origin O2 of macro 200.
As a result, for example, as illustrated in FIG. 3 (FIG. 3 illustrates a case where origin O2 of macro 200 and origin O1 of chip 100 differ in the X-axis (horizontal) direction), in spite of the fact that the layout data passes the density verification at the macro level (200) with no error (OK) in N-1 and N steps, when the density verification is performed at the chip level (100) where the macro is loaded in X step, a density error (a pseudo error due to density exceeding a maximum density) occurs due to difference of how patterns are included in the density verification frame W resulting from difference of the starting origins.
More specifically, in the example of FIG. 3, in the circumference (the left and right ends) of density verification frame W, even though a metal pattern (metal trace) M101 is included in density verification frame W in macro-level N-1 step and a metal pattern M102 is included in density verification frame W in macro-level N step so that the density verification is OK (for example, trace density is less than or equal to a maximum density 60%), for example, in chip-level X step, both metal patterns M101 and M102 may be included in density verification frame W so as to cause an error in the density verification. (For example, the trace density exceeds the maximum density 60%.) It is because the macro is typically prepared just below the upper limit of the density standard.
Then, in the conventional art, if the density error occurs in the chip-level density verification as described above, the process returns the macro level (returns to macro correction) to correct the macro for each product type so as to pass the chip-level density verification and, therefore, a man-hour is used every time the macro is corrected. Further, in such approach, when the same macro is loaded on another product type, the error may occur again and, therefore, this approach does not solve the problem.
In order to address this problem, as a technique for satisfying the density verification standard without returning to the macro correction, it is considered to make the step width smaller (finer) in the macro-level density verification. FIG. 4 illustrates an example in which the step width is changed from 10 μm in the above example to 1.0 μm.
As illustrated in FIG. 4, for example, in the macro-level density verification, when the step width is 1.0 μm, it is seen that, even in the region where no error is detected in (N-1 and N steps), an error is detected in (N′ step).
However, in the macro-level density verification, in order to satisfy the density verification standard by simply reducing the step width, the step width is reduced up to a minimum grid (for example, 5 nm) in a design rule used for manufacturing the semiconductor device, but, such fine step width is practically impossible because of enormous time for the density verification.
Thus, properly speaking, at the macro level, the density verification may be satisfied from an infinite number of starting origins (or, in other words, with the verification frame disposed at an arbitrary position), but such verification may not be implemented due to constraints of TAT (turn around time) and tools and, in reality, the verification is performed from only one origin. Therefore, the density standard may not be satisfied in the verification frame at some of arbitrary starting points existing between adjacent steps and, as a result, there are regions where the verification is insufficient. Further, it is not practical to make the step width smaller because it directly increases time for the density verification.
Therefore, in the conventional layout data verification method (program) for the semiconductor device, when the macro is prepared just below the upper limit of density, there is a possibility to cause the density error at the macro level in the verification from starting origins other than one specific starting origin.